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DS89C450 Evaluation Kit
Serial Ports
Both serial ports of the DS89C450 (Serial Port 0 and Serial Port 1) are translated to RS-232 levels and brought out
to DB9 connectors at J2 and J3. Serial Port 0 (J2) must always be used when communicating with the bootloader.
Memory
The external memory of the DS89C450 on this EV kit is designed to operate with the address and data bus
multiplexed on P0 and P2. A 128kB x 8 SRAM is installed, which is accessed as both program and data memory
by this multiplexed bus. Note that as the total memory space of the DS89C450 is only 64kB of program memory
and 64K of data memory, port pin memory banking must be used to access the entire 128kB-memory space.
CPLD
The CPLD device on the EV kit board is preprogrammed to perform several functions.
?
?
?
Address latching of the low 8 bits of the external memory address from port P0.
Mapping together program and data memory.
Performing port pin memory banking (optional).
The RTL code preprogrammed into the CPLD is as follows.
module Eval(AD, nRD, ALE, nPSEN, CFG0, CFG1, SW_IN, P1, A, A16, A17, nOE, SW_OUT);
input
input
input
input
input
input
input
[7:0] AD;
nRD;
ALE;
nPSEN;
CFG0;
CFG1;
SW_IN;
//
//
//
//
//
//
//
Multiplexed low-order address and data from micro
Data memory read enable from micro
Address latch enable from micro
Program memory read enable from micro
Configuration input zero (from DIP switch)
Configuration input one (from DIP switch)
Interrupt switch input (from pushbutton)
inout
[7:0] P1;
// Port 1 from micro
output [7:0] A;
output A16;
output A17;
output nOE;
output SW_OUT;
reg
[7:0] A;
//
//
//
//
//
Demultiplexed low-order address to RAM
Address line to RAM
Address line to RAM
Output enable to RAM
Interrupt switch output (to micro)
always @(negedge ALE) begin
A <= AD;
end
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
A16
A17
P1[0]
P1[1]
P1[2]
P1[3]
P1[4]
P1[5]
P1[6]
P1[7]
nOE
SW_OUT
=
=
=
=
=
=
=
=
=
=
=
=
(CFG0 == 0) ?
(CFG0 == 0) ?
(CFG1 == 0) ?
(CFG1 == 0) ?
(CFG1 == 0) ?
(CFG1 == 0) ?
(CFG1 == 0) ?
(CFG1 == 0) ?
(CFG1 == 0) ?
(CFG1 == 0) ?
nRD & nPSEN;
SW_IN;
P1[0] : 1'b0;
P1[1] : 1'b0;
SW_IN : 1'bz;
SW_IN : 1'bz;
SW_IN : 1'bz;
SW_IN : 1'bz;
~SW_IN : 1'bz;
~SW_IN : 1'bz;
~SW_IN : 1'bz;
~SW_IN : 1'bz;
endmodule
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